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	<title>Intel Software Network Blogs</title>
	
	<link>http://software.intel.com/en-us/blogs</link>
	<description />
	<pubDate>Mon, 13 Oct 2008 20:26:12 +0000</pubDate>
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	<language>en</language>
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		<title>Reminder: vPro Developer Bootcamp is on Oct 15th</title>
		<link>http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~3/419852574/</link>
		<comments>http://software.intel.com/en-us/blogs/2008/10/13/reminder-vpro-developer-bootcamp-is-on-oct-15th/#comments</comments>
		<pubDate>Mon, 13 Oct 2008 20:26:12 +0000</pubDate>
		<dc:creator>Ajay Mungara (Intel)</dc:creator>
		
		<category><![CDATA[Manageability]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2008/10/13/reminder-vpro-developer-bootcamp-is-on-oct-15th/</guid>
		<description><![CDATA[First of all thanks to all of you who have already registered to the event and giving us your feedback to make this event more relevant to you. It is not too late, there is still time to register for the Intel vPro Developer Bootcamp. The goal of the boot camp is to jump start [...]]]></description>
			<content:encoded><![CDATA[<p>First of all thanks to all of you who have already registered to the event and giving us your feedback to make this event more relevant to you. It is not too late, there is still time to register for the <a href="http://events.unisfair.com/index.jsp?eid=315&amp;seid=30">Intel vPro Developer Bootcamp.</a> The goal of the boot camp is to jump start your software development for the Third Generation of Intel® CoreTM2  processor with vProTM technology. Get an overview of the Intel Active Management  Technology (Intel AMT) and all new features in the Intel AMT 4.0/5.0.</p>
<p>I wanted to remind all of you that the live event is scheduled for Wednesday, Oct 15th, 8AM-3PM PST. The event will also be archived for the next 30 days, but there will be no live Q&amp;A and networking opportunity in the archived event.The event is a virtual experience with technical sessions, ISV/Intel exhibition hall, networking lounge, etc. I am looking forward to seeing you at the Boot Camp. Also, please don't forget to give us your feedback - Your feedback is very important to us and can help us host better events in the future.</p>
<p><a href="http://events.unisfair.com/index.jsp?eid=315&amp;seid=30"><img class="alignleft size-medium wp-image-3410" title="Main Hall" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2008/10/main2-300x165.jpg" alt="" width="300" height="165" /></a> <a href="http://events.unisfair.com/index.jsp?eid=315&amp;seid=30"><img class="alignright size-medium wp-image-3411" title="Exhibition Hall" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2008/10/exhibitionhall-300x164.jpg" alt="" width="300" height="164" /></a></p>
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		<title>Microsoft Silverlight 2.0 Released</title>
		<link>http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~3/419730742/</link>
		<comments>http://software.intel.com/en-us/blogs/2008/10/13/microsoft-silverlight-20-released/#comments</comments>
		<pubDate>Mon, 13 Oct 2008 18:04:22 +0000</pubDate>
		<dc:creator>Doug Holland (Intel)</dc:creator>
		
		<category><![CDATA[Software Engineering]]></category>

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		<description><![CDATA[Microsoft today released Silverlight 2.0 to manufacturing and you can read about the release on S. “Soma” Somsegar's blog and then download the release from the Silverlight homepage later today.
]]></description>
			<content:encoded><![CDATA[<p>Microsoft today released <a href="http://www.microsoft.com/silverlight/default.aspx" target="_blank">Silverlight 2.0</a> to manufacturing and you can read about the release on <a href="http://blogs.msdn.com/somasegar/archive/2008/10/13/silverlight-2-released.aspx" target="_blank">S. “Soma” Somsegar's blog</a> and then download the release from the <a href="http://www.microsoft.com/silverlight/default.aspx" target="_blank">Silverlight</a> homepage later today.</p>
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		<title>TBB containers vs. STL. Functionality rift</title>
		<link>http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~3/419396788/</link>
		<comments>http://software.intel.com/en-us/blogs/2008/10/13/tbb-containers-vs-stl-functionality-rift/#comments</comments>
		<pubDate>Mon, 13 Oct 2008 10:28:29 +0000</pubDate>
		<dc:creator>Andrey Marochko (Intel)</dc:creator>
		
		<category><![CDATA[Multicore]]></category>

		<category><![CDATA[Threading Building Blocks]]></category>

		<category><![CDATA[concurrent container]]></category>

		<category><![CDATA[container]]></category>

		<category><![CDATA[STL]]></category>

		<category><![CDATA[TBB]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2008/10/13/tbb-containers-vs-stl-functionality-rift/</guid>
		<description><![CDATA[How TBB concurrent containers differ from the STL ones, why the particular design decisions were made, and what the efficiency of both approaches depends on...]]></description>
			<content:encoded><![CDATA[<p><!--[if gte mso 9]&gt;  Normal 0   false false false         MicrosoftInternetExplorer4  &lt;![endif]--><!--[if gte mso 9]&gt;   &lt;![endif]--><!--  /* Font Definitions */  @font-face 	{font-family:SimSun; 	panose-1:2 1 6 0 3 1 1 1 1 1; 	mso-font-alt:宋体; 	mso-font-charset:134; 	mso-generic-font-family:auto; 	mso-font-pitch:variable; 	mso-font-signature:3 135135232 16 0 262145 0;} @font-face 	{font-family:"\@SimSun"; 	panose-1:2 1 6 0 3 1 1 1 1 1; 	mso-font-charset:134; 	mso-generic-font-family:auto; 	mso-font-pitch:variable; 	mso-font-signature:3 135135232 16 0 262145 0;}  /* Style Definitions */  p.MsoNormal, li.MsoNormal, div.MsoNormal 	{mso-style-parent:""; 	margin:0cm; 	margin-bottom:.0001pt; 	mso-pagination:widow-orphan; 	font-size:12.0pt; 	font-family:"Times New Roman"; 	mso-fareast-font-family:SimSun;} a:link, span.MsoHyperlink 	{color:blue; 	text-decoration:underline; 	text-underline:single;} a:visited, span.MsoHyperlinkFollowed 	{color:purple; 	text-decoration:underline; 	text-underline:single;} p 	{mso-margin-top-alt:auto; 	margin-right:0cm; 	mso-margin-bottom-alt:auto; 	margin-left:0cm; 	mso-pagination:widow-orphan; 	font-size:12.0pt; 	font-family:"Times New Roman"; 	mso-fareast-font-family:SimSun;} @page Section1 	{size:612.0pt 792.0pt; 	margin:2.0cm 42.5pt 2.0cm 3.0cm; 	mso-header-margin:36.0pt; 	mso-footer-margin:36.0pt; 	mso-paper-source:0;} div.Section1 	{page:Section1;}  /* List Definitions */  @list l0 	{mso-list-id:1028338794; 	mso-list-template-ids:-401338462;} @list l0:level1 	{mso-level-number-format:bullet; 	mso-level-text:; 	mso-level-tab-stop:36.0pt; 	mso-level-number-position:left; 	text-indent:-18.0pt; 	mso-ansi-font-size:10.0pt; 	font-family:Symbol;} ol 	{margin-bottom:0cm;} ul 	{margin-bottom:0cm;} --><!--[if gte mso 10]&gt; &lt;!   /* Style Definitions */  table.MsoNormalTable 	{mso-style-name:"Table Normal"; 	mso-tstyle-rowband-size:0; 	mso-tstyle-colband-size:0; 	mso-style-noshow:yes; 	mso-style-parent:""; 	mso-padding-alt:0cm 5.4pt 0cm 5.4pt; 	mso-para-margin:0cm; 	mso-para-margin-bottom:.0001pt; 	mso-pagination:widow-orphan; 	font-size:10.0pt; 	font-family:"Times New Roman"; 	mso-ansi-language:#0400; 	mso-fareast-language:#0400; 	mso-bidi-language:#0400;} --> <!--[endif]--></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;">I've noticed that developers who start using TBB often ask questions "Whether I should replace STL containers (protected with locks where necessary) by their TBB counterparts in my application? Are TBB containers faster that those from STL?". Unfortunately questions formulated like this are too general to get a specific answer. Therefore I decided to make a concise overview of how TBB concurrent containers differ from the STL ones, why the particular design decisions were made, and what the efficiency of both approaches depends on (though I'm not a person who designed TBB containers I believe my understanding of the matter is basically sound, and </span><!--[if gte mso 9]&gt;  Normal 0   false false false         MicrosoftInternetExplorer4  &lt;![endif]--><!--[if gte mso 9]&gt;   &lt;![endif]--><!--  /* Font Definitions */  @font-face 	{font-family:SimSun; 	panose-1:2 1 6 0 3 1 1 1 1 1; 	mso-font-alt:宋体; 	mso-font-charset:134; 	mso-generic-font-family:auto; 	mso-font-pitch:variable; 	mso-font-signature:3 135135232 16 0 262145 0;} @font-face 	{font-family:"\@SimSun"; 	panose-1:2 1 6 0 3 1 1 1 1 1; 	mso-font-charset:134; 	mso-generic-font-family:auto; 	mso-font-pitch:variable; 	mso-font-signature:3 135135232 16 0 262145 0;}  /* Style Definitions */  p.MsoNormal, li.MsoNormal, div.MsoNormal 	{mso-style-parent:""; 	margin:0cm; 	margin-bottom:.0001pt; 	mso-pagination:widow-orphan; 	font-size:12.0pt; 	font-family:"Times New Roman"; 	mso-fareast-font-family:SimSun;} @page Section1 	{size:612.0pt 792.0pt; 	margin:2.0cm 42.5pt 2.0cm 3.0cm; 	mso-header-margin:36.0pt; 	mso-footer-margin:36.0pt; 	mso-paper-source:0;} div.Section1 	{page:Section1;} --><!--[if gte mso 10]&gt; &lt;!   /* Style Definitions */  table.MsoNormalTable 	{mso-style-name:"Table Normal"; 	mso-tstyle-rowband-size:0; 	mso-tstyle-colband-size:0; 	mso-style-noshow:yes; 	mso-style-parent:""; 	mso-padding-alt:0cm 5.4pt 0cm 5.4pt; 	mso-para-margin:0cm; 	mso-para-margin-bottom:.0001pt; 	mso-pagination:widow-orphan; 	font-size:10.0pt; 	font-family:"Times New Roman"; 	mso-ansi-language:#0400; 	mso-fareast-language:#0400; 	mso-bidi-language:#0400;} --> <!--[endif]--><span style="Arial;">in the worst case </span><span style="Arial;">my colleagues will correct me if I misstate anything:) ). </span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;"> </span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;">I'll try to keep this discussion general enough, without delving into the implementation details or analysis of specific use cases, so that after reading it you have an understanding, which criteria should be taken into account when choosing the solution for your particular application.</span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;"> </span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;">Let's have a look at how do the scopes of functionality of both container libraries correlate with each other.</span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;"> </span></p>
<p><span style="Arial;">First of all one have to understand that despite of similar names and a lot of commonality in interfaces of TBB and STL containers, the former are not simply thread-safe versions of the latter. Though we tried to make TBB interfaces as close as possible to those of STL, most of them still have substantial differences in their usage models (and consequently in interfaces). To name the most prominent ones:</span></p>
<p><span style="Arial;">- concurrent      vector does not support insert and erase operations (new items can only be      pushed back), and cannot be shrunk;</span><br />
<span style="Arial;">- concurrent      hash map does not support iterators, and uses accessors instead.</span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;"> </span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;">There are two main reasons why concurrent containers cannot be made thread-safe replicas of their STL counterparts. First, concurrent access invalidates some of the assumptions that the serial code relies on. Let's consider vector's method pop_back(). In the serial code it is often used as part of the following idiom:</span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;"><span> </span>T item = v.back();</span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;"><span> </span>v.pop_back();</span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;">But in concurrent case another thread may pop the same item while the first thread is in between of the two above operations. </span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;"> </span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;">Leaving such methods in the TBB interface would encourage TBB users to inadvertently write inherently flawed code. Such adverse scenarios would be quite probable since most of the programmers move to writing parallel code after getting substantial experience with the serial programming and its patterns. Another risk is that such unsafe methods would mask dangerous pieces of serial code when it is parallelized. Taking all this into account TBB designers decided to explicitly prohibit use cases that lose their original serial meaning or lead to indeterministic behavior in the multithreaded apps.</span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;"> </span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;">The fact that TBB culled STL interfaces still does not mean that what remains is a thread-safe subset of STL functionality. Some operations in TBB containers are not thread safe, like reserve() and clear() in concurrent vector. Other methods are extensions to what STL has and reflect the specifics of the parallel usage models, e.g. the family of grow_xxx() methods in the concurrent vector or pop_if_present() and push_if_not_full() of concurrent queue. </span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;"> </span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;">Besides, some of the concepts though supported by concurrent containers may change their meaning slightly in comparison to their serial usage. For example the intuitively simple "first in first out" notion becomes somewhat fuzzy when a value may be pushed by one thread and popped by another. So before starting incorporating concurrent containers into your application for the first time, please read the reference (or at least tutorial) carefully, to avoid unpleasant surprises.</span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;"> </span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;">The second reason why the usage models of TBB and STL containers differ is more mundane. Actually it is what the whole multicore shift is about, … right, it's performance. Supporting some of the serial usage models though technically possible would be so inefficient that their applicability area would become marginally small (e.g. iterating over the concurrent hash map). </span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;"> </span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;">Besides, from the methodology standpoint, providing such tremendously inefficient APIs would entice unaware developers into writing code that covertly ruins performance of their applications, and increase the probability of the situations when a serial code that apparently has been successfully parallelized, works slower than its serial ancestor even on a quad-core machine.</span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;"> </span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;">At last, some of the dropped functionality, if implemented, would have taken unbearably heavy toll on the performance of other operations, and thus render the whole concurrent container next to useless. For example, insert() in concurrent vector, if allowed, would have drastically burdened both iterating and growing operations, which constitute the backbone of the container's usage model.</span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;"> </span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;">Now that you have a general idea why TBB concurrent containers are quite unlike even their closest STL relatives, I'd like to attract your attention to the fact that TBB (at least so far) provides noticeably fewer containers than STL does. I believe most of you have already guessed why it is so (disregarding the considerations of TBB team's limited resources). Anyway I'd recommend you to have a look at the blog discussing one particular case of not supported containers: <a href="../../2007/12/20/linked-lists-incompatible-with-parallel-programming/">"Linked Lists - Incompatible with Parallel Programming?"</a>.</span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;"> </span></p>
<p style="0cm 0cm 0.0001pt;"><span style="Arial;">Though I’ve already lavishly used words “performance” and “efficiency”, all that was said before does not give any clue as to which choice should you do in your particular application (and I promised that you’ll learn it (well, at least will have an idea)). I’m not going back on my words, and we’ll talk about it in my next post that will get to you sooner rather than later (hopefully before the end of this week). Cheers.</span></p>
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		<item>
		<title>More configurations (disabling) of the Intel AMT icon. Part 4 in the Intel AMT software series</title>
		<link>http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~3/419001415/</link>
		<comments>http://software.intel.com/en-us/blogs/2008/10/12/more-configurations-disabling-of-the-intel-amt-icon-part-4-in-the-intel-amt-software-series/#comments</comments>
		<pubDate>Mon, 13 Oct 2008 00:14:18 +0000</pubDate>
		<dc:creator>Shmuel Gershon (Intel)</dc:creator>
		
		<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2008/10/12/more-configurations-disabling-of-the-intel-amt-icon-part-4-in-the-intel-amt-software-series/</guid>
		<description><![CDATA[Hi!
In the previous part of this series (part 1, part 2, part 3), we began describing the Intel AMT software, and the ways in which the Intel AMT System Status can be configured to suit a specific system, network or style.
As we wrote in the past, this application unnoficially goes also by the names of or [...]]]></description>
			<content:encoded><![CDATA[<p>Hi!<br />
In the previous part of this series (<em><a title="Part 1" href="http://software.intel.com/en-us/blogs/2008/07/20/the-software-bundled-with-intel-amt-part-1-2/" target="_blank">part 1</a>, <a title="Part 2" href="http://software.intel.com/en-us/blogs/2008/09/15/intel-amt-sw-part-2-the-notification-area-icon-understanding-the-pop-up/" target="_blank">part 2</a>, <a title="Part 3" href="http://software.intel.com/en-us/blogs/2008/09/23/configuring-the-notification-area-icon-amp-app-intel-amt-sw-part-3/" target="_blank">part 3</a></em>), we began describing the Intel AMT software, and the ways in which the <strong>Intel AMT System Status</strong> can be configured to suit a specific system, network or style.</p>
<p>As we wrote in the past, this application unnoficially goes also by the names of or <strong>Intel AMT pop-up </strong>or <strong>Privacy Icon</strong>. But unfortunately it is also called by some people with the name of '<em>annoying</em>' :(. This may be because a manufacturer set it to 'always popup', or because it displays an error message (<em>see how to fix the error in the <a title="Previous Post" href="http://software.intel.com/en-us/blogs/2008/09/23/configuring-the-notification-area-icon-amp-app-intel-amt-sw-part-3/" target="_blank">previous post</a></em>)…  But the fact is that it is considered bothersome by a number of users.<br />
For those, this time we'll see how the icon can be minimized, disabled or removed from the system. Just keep in mind the notes at the end of the article, our recommendation is to have it minimized at startup.</p>
<p>Here too, the notes apply:<br />
<strong>Note 1: </strong>Your systems may use a different folder for the software, change it accordingly where needed.<br />
<strong>Note 2: </strong>Some modifications include changing values in the registry. While this should be inoffensive when done on the key/values described below, the registry is a dangerous place to tamper. Do it with care and at your own risk. :)<br />
<strong>Note 3: </strong>The instructions below pertain to versions of the software up to Intel AMT 3.0. Versions 4.0 and on will be discussed in a different post.</p>
<ul>
<li><strong>Minimize the icon on startup</strong><br />
Your application should appear minimized when Windows loads. The icon will be seen in the notification area, but no other distracting dialog will appear -- until the notification area icon is double clicked.<br />
This is the best option to go. It keeps the application there in case it is needed, but it is out of the way.The following registry key determines the loading behavior:<br />
<em>Key: [HKEY_LOCAL_MACHINE\SOFTWARE\Intel\Network_Services\atchk]<br />
Value: "MinimizePrivacyIconAtStart"=dword:00000001<br />
</em><br />
Have it set to 00000001 to minimize on start, or 00000000 to have it popup.</li>
</ul>
<ul>
<li><strong>Disable loading of the application</strong><br />
If you want the application not to load at all, you can delete it from the startup list, by deleting its value at the following registry setting:<br />
<em>Key: [HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Windows\CurrentVersion\Run]<br />
Value: "atchk"="\"C:\\Program Files\\Intel\\AMT Status\\atchk.exe\""<br />
</em> <br />
Delete the value, as below, to prevent the app from loading.<br />
<em>Key: [HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Windows\CurrentVersion\Run]<br />
Value: "atchk"=""</em></li>
</ul>
<ul>
<li><strong>Disabling the Intel® AMT System Status icon completely</strong><br />
It was <a title="Post by Ajay" href="http://software.intel.com/en-us/blogs/2007/04/26/instructions-to-disable-the-intel-amt-privacy-notification-popup/" target="_blank">suggested in the past </a>that one of the ways to disable the Intel AMT dialog is by simply telling Windows not to load it, in 'msconfig'. If that's what you want, here's the proper way to do it:<br />
Run 'msconfig' from the 'Run…' dialog, just go to the 'Services' and 'Startup' tabs and <span style="underline;">unselect</span> the <strong>Intel® AMT System Status Service</strong> and the <strong>Intel® AMT System Status</strong>.<br />
 <br />
Just the 2 lines shown in the pictures below (<em>unrelated apps purposely blurred</em>).<br />
<img class="alignnone size-full wp-image-3320" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2008/10/msconfig1.jpg" alt="" width="499" height="337" /><br />
<img class="alignnone size-full wp-image-3321" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2008/10/msconfig2.jpg" alt="" width="500" height="335" /><br />
Do not uncheck other Intel services and applications, as they may be of importance to your system's function and performance.</li>
</ul>
<p> <br />
<strong>Very Important Note!</strong> Pay attention that by disabling the icon on startup or disabling the application and service completely, you take from the transparency and straightforwardness of the system.<br />
<code>Depending on the context, this may also have serious disclosure, privacy and/or legal implications.</code><br />
Most times the users will be interested to know if the manageability system is performing in their systems. <strong>So the recommended option is to set "minimize icon at startup"</strong> - in this way, the Intel AMT popup is not intrusive/obtrusive, and the users still have access to up-to-date and transparent system information.</p>
<p>Well, that's it for the System Status icon. A lot of configurations, for such a little application :)<br />
Next times we'll see what are the UNS, LMS and Intel MEI are about -- stay tuned, ask your questions.</p>
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		<item>
		<title>Jeffrey Snover, Martin Fowler and Neil Ford: Domain Specific Languages</title>
		<link>http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~3/417098924/</link>
		<comments>http://software.intel.com/en-us/blogs/2008/10/10/jeffrey-snover-martin-fowler-and-neil-ford-domain-specific-languages/#comments</comments>
		<pubDate>Fri, 10 Oct 2008 19:34:44 +0000</pubDate>
		<dc:creator>Doug Holland (Intel)</dc:creator>
		
		<category><![CDATA[Software Engineering]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2008/10/10/jeffrey-snover-martin-fowler-and-neil-ford-domain-specific-languages/</guid>
		<description><![CDATA[Jeffrey Snover, Martin Fowler and Neil Ford: Domain Specific Languages

Over on MSDN's Channel 9 is an interesting conversation between Jeffrey Snover, Martin Fowler, and Neil Ford on Domain Specific Languages.  
For most of you reading this blog Martin Fowler (Thoughtworks) needs no introductions and if you don't know who he is he is the one responsible for the [...]]]></description>
			<content:encoded><![CDATA[<p><a id="ctl00_MainPlaceHolder_Starter_TitleLink" href="http://software.intel.com/posts/Charles/Jeffrey-Snover-Martin-Fowler-and-Neil-Ford-Domain-Specific-Languages/">Jeffrey Snover, Martin Fowler and Neil Ford: Domain Specific Languages</a></p>
<p><a href="http://channel9.msdn.com/posts/Charles/Jeffrey-Snover-Martin-Fowler-and-Neil-Ford-Domain-Specific-Languages/"><img class="alignnone size-medium wp-image-3395" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2008/10/martin-fowler-300x224.jpg" alt="" width="300" height="224" /></a></p>
<p>Over on MSDN's <a href="http://channel9.msdn.com" target="_blank">Channel 9</a> is an interesting conversation between Jeffrey Snover, <a href="http://www.martinfowler.com/" target="_blank">Martin Fowler</a>, and <a href="http://www.thoughtworks.com/who-we-are/our-people/profiles/Ford,+Neal.html" target="_blank">Neil Ford</a> on Domain Specific Languages.  </p>
<p>For most of you reading this blog <a href="http://www.martinfowler.com/" target="_blank">Martin Fowler</a> (<a href="http://www.thoughtworks.com" target="_blank">Thoughtworks</a>) needs no introductions and if you don't know who he is he is the one responsible for the Refactor menu within an IDE such as Visual Studio or Eclipse. If you don't already have a copy of his book <a href="http://www.amazon.com/gp/redirect.html?ie=UTF8&amp;location=http%3A%2F%2Fwww.amazon.com%2FRefactoring-Improving-Existing-Addison-Wesley-Technology%2Fdp%2F0201485672%3Fie%3DUTF8%26s%3Dbooks%26qid%3D1223666743%26sr%3D8-2&amp;tag=sofbloint-20&amp;linkCode=ur2&amp;camp=1789&amp;creative=9325" target="_blank">Refactoring</a> then definitely check it out. </p>
<p>Neil Ford is a Software Architect and Mean Wrangler with <a href="http://www.thoughtworks.com" target="_blank">Thoughtworks</a>, listen to the conversation and you'll find out it actually says that on his business cards.</p>
<p><a href="http://blogs.msdn.com/powershell/default.aspx" target="_blank">Jeffrey Snover</a> is a Software Architect at Microsoft and the creator of the Windows <a href="http://blogs.msdn.com/powershell/default.aspx" target="_blank">PowerShell</a>.</p>
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		<item>
		<title>WebUI issues with IE and AD</title>
		<link>http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~3/417089552/</link>
		<comments>http://software.intel.com/en-us/blogs/2008/10/10/webui-issues-with-ie-and-ad/#comments</comments>
		<pubDate>Fri, 10 Oct 2008 19:29:31 +0000</pubDate>
		<dc:creator>Lance Atencio (Intel)</dc:creator>
		
		<category><![CDATA[Manageability]]></category>

		<category><![CDATA[Active Directory]]></category>

		<category><![CDATA[AMT]]></category>

		<category><![CDATA[Internet Explorer]]></category>

		<category><![CDATA[WebUI]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2008/10/10/webui-issues-with-ie-and-ad/</guid>
		<description><![CDATA[If you have extended Active Directory (AD) for use with your AMT clients you may have issues connecting to the AMT WebUI for those machines using Internet Explorer (IE). This is related to authentication settings.
If you experience this problem, you can first try another browser (e.g. Firefox) to see if you can connect to the [...]]]></description>
			<content:encoded><![CDATA[<p>If you have extended Active Directory (AD) for use with your AMT clients you may have issues connecting to the AMT WebUI for those machines using Internet Explorer (IE). This is related to authentication settings.</p>
<p>If you experience this problem, you can first try another browser (e.g. Firefox) to see if you can connect to the WebUI. If successful, then you can try the setting the following configurations in your IE settings.</p>
<li>In IE, go to Tools &gt; Internet options &gt; Security &gt; Custom level &gt; User Authentication – Prompt for user name and password</li>
<li>In IE, go to Tools &gt; Internet options &gt; Advanced &gt; Security – Enable Integrated Windows Authentication</li>
<p>When I  first encountered this issue I thought it was a bit obscure, but now am surprised it is not being reported more often.</p>
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		<item>
		<title>Anders Hejlsberg and Guy Steele: Concurrency and Language Design</title>
		<link>http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~3/416946988/</link>
		<comments>http://software.intel.com/en-us/blogs/2008/10/10/anders-hejlsberg-and-guy-steele-concurrency-and-language-design/#comments</comments>
		<pubDate>Fri, 10 Oct 2008 16:36:16 +0000</pubDate>
		<dc:creator>Doug Holland (Intel)</dc:creator>
		
		<category><![CDATA[Software Engineering]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2008/10/10/anders-hejlsberg-and-guy-steele-concurrency-and-language-design/</guid>
		<description><![CDATA[Anders Hejlsberg and Guy Steele: Concurrency and Language Design

Given the multi-core revolution, which Intel is without a doubt the driving force behind, I am very interested to learn more about how Microsoft and others intend to enable architects and developers to more efficiently write multithreaded code. MSDN's Channel 9 has an interesting conversation with Anders Hejlsberg [...]]]></description>
			<content:encoded><![CDATA[<p><a id="ctl00_MainPlaceHolder_EntryList_ctl05_EntryTemplate_TitleLink" href="http://software.intel.com/posts/Charles/Anders-Hejlsberg-and-Guy-Steele-Concurrency-and-Language-Design/">Anders Hejlsberg and Guy Steele: Concurrency and Language Design</a></p>
<p><a href="http://channel9.msdn.com/posts/Charles/Anders-Hejlsberg-and-Guy-Steele-Concurrency-and-Language-Design/"><img class="alignnone size-medium wp-image-3392" src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2008/10/andersh-300x224.jpg" alt="" width="300" height="224" /></a></p>
<p>Given the multi-core revolution, which Intel is without a doubt the driving force behind, I am very interested to learn more about how Microsoft and others intend to enable architects and developers to more efficiently write multithreaded code. MSDN's Channel 9 has an interesting conversation with <a href="http://www.microsoft.com/presspass/exec/techfellow/Hejlsberg/default.mspx" target="_blank">Anders Hejlsberg</a> and <a href="http://research.sun.com/people/mybio.php?uid=25706" target="_blank">Guy Steele</a> where they discuss <a href="http://channel9.msdn.com/posts/Charles/Anders-Hejlsberg-and-Guy-Steele-Concurrency-and-Language-Design/" target="_blank">concurrency and language design</a>. <a href="http://www.microsoft.com/presspass/exec/techfellow/Hejlsberg/default.mspx" target="_blank">Anders Hejlsberg</a>, for those who don't know him, is the architect at Microsoft of the C# programming Language. <a href="http://research.sun.com/people/mybio.php?uid=25706" target="_blank">Guy Steele</a> is a language architect from <a href="http://www.sun.com" target="_blank">Sun Microsystems</a> and is working on a new language called <a href="http://projectfortress.sun.com/Projects/Community" target="_blank">Fortress</a> which features implicit parallelism.</p>
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		<item>
		<title>Eliminate False Sharing? Wrong!</title>
		<link>http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~3/416319870/</link>
		<comments>http://software.intel.com/en-us/blogs/2008/10/09/eliminate-false-sharing-wrong/#comments</comments>
		<pubDate>Fri, 10 Oct 2008 01:29:09 +0000</pubDate>
		<dc:creator>Dmitriy V'jukov</dc:creator>
		
		<category><![CDATA[Multicore]]></category>

		<category><![CDATA[Software Engineering]]></category>

		<category><![CDATA[cache]]></category>

		<category><![CDATA[data layout]]></category>

		<category><![CDATA[false-sharing]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2008/10/09/eliminate-false-sharing-wrong/</guid>
		<description><![CDATA[Entry in Parallel Programming with .NET blog "Most Common Performance Issues in Parallel Programs" and recent article in MSDN ".NET Matters: False Sharing" have attracted my attention. Basically they both suggest to eliminate false sharing. Wrong! Wrong! Wrong! It's not the whole truth, so to say. So if authors were under oath in the virtual [...]]]></description>
			<content:encoded><![CDATA[<p>Entry in Parallel Programming with .NET blog "<a href="http://blogs.msdn.com/pfxteam/archive/2008/08/12/8849984.aspx">Most Common Performance Issues in Parallel Programs</a>" and recent article in MSDN "<a href="http://msdn.microsoft.com/en-us/magazine/cc872851.aspx">.NET Matters: False Sharing</a>" have attracted my attention. Basically they both suggest to eliminate false sharing. Wrong! Wrong! Wrong! It's not the whole truth, so to say. So if authors were under oath in the virtual IT court, they would have to be arrested. Fortunately they weren't under oath :)</p>
<p>The first thing one has to say in that context is:<br />
1. <strong>Eliminate sharing</strong>. Period. Not false sharing, just sharing. It's sharing that has huge performance penalties. It's sharing that changes linear scalability of your application to super-linear degradation. And believe me, hardware has no means to distinguish false sharing from true sharing. It can't penalize only false sharing, and handle true sharing without any performance penalties.</p>
<p>Second thing one has to say in that context is:<br />
2. Put things that must be close to each other... <strong>close to each other</strong>. Assume following situation. In order to complete some operation thread has to update variable X and variable Y. If variables are situated far from each other (on different cache lines), then thread has to load (from main memory, or from other processor's cache) 2 cache lines instead of 1 (if variables are situated close to each other). Effectively this situation can be considered the same as false-sharing, because thread places unnecessary work on interconnects, thus degrading performance and scalability.</p>
<p>Points 1 and 2 can be aggregated as:</p>
<p>1+2. <strong>Do pay attention to data layout</strong>. This was important in the 60's. This is even more important in the multicore era.</p>
<p>Only after that one can also add:</p>
<p>3. Sometimes sharing can show up when you are not expecting it, i.e <strong>false sharing</strong>. This is important to eliminate false sharing too... etceteras... [insert here contents of <a href="http://msdn.microsoft.com/en-us/magazine/cc872851.aspx">False Sharing</a> article]</p>
<p>If one says <strong>only </strong>point 3, well, it's basically senseless. And sometimes it can even hurt.</p>
<p>Let's consider simple example:</p>
<blockquote>
<pre>long volatile g_operation_count = 0;</pre>
<pre>void collect_statistics() {</pre>
<pre>  InterlockedIncrement(&amp;g_operation_count);
}</pre>
</blockquote>
<p>What does naive programmer think about it? <em>Hmmm... Let's see... I use "fast" non-blocking interlocked operations. Good!... Hmmm... False sharing. Let's see... Hmmm... Here is no false sharing. Good! So my program fully conforms to recommendations of experts.</em></p>
<p>Rubbish! It's a dead-slow, completely non-scalable program.</p>
<p>Now let's apply consistent rules to the example. First of all we have to do something like this:</p>
<blockquote>
<pre style="30px;">long volatile g_operation_count [MAX_THREAD_COUNT] = {};</pre>
<pre style="30px;">void collect_statistics() {</pre>
<pre style="30px;">  InterlockedIncrement(&amp;g_operation_count[get_current_thread_id()]);
}</pre>
</blockquote>
<p>It's good distributed design. When we need aggregate number of operations we just sum up all thread local counters.</p>
<p>Only at this point we can remember about false-sharing and put the final touches to the code:</p>
<blockquote>
<pre style="30px;">struct counter_t {
  long volatile count;
  char pad [CACHE_LINE_SIZE - sizeof(long)];
}
counter_t g_operation_count [MAX_THREAD_COUNT] = {};</pre>
<pre style="30px;">void collect_statistics() {</pre>
<pre>  InterlockedIncrement(&amp;g_operation_count[get_current_thread_id()].count);
}</pre>
</blockquote>
<p>Ok, this distributed version is also fast and scalable. It has linear scalability and can be faster up to 100x on modern multi-core hardware as compared with original version.</p>
<p>So, point 1+2 is a kind of general rule, while point 3 is just a refinement to them.</p>
<p>Why people don't say the whole truth? I don't know. I don't beleive that authors don't aware of the problem. Maybe they think that it's obvious. The practice shows that it's not...</p>
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		<item>
		<title>Hello, Intel Software Network!</title>
		<link>http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~3/416306013/</link>
		<comments>http://software.intel.com/en-us/blogs/2008/10/09/hello-intel-software-network/#comments</comments>
		<pubDate>Fri, 10 Oct 2008 01:27:35 +0000</pubDate>
		<dc:creator>Dmitriy V'jukov</dc:creator>
		
		<category><![CDATA[Multicore]]></category>

		<category><![CDATA[Software Engineering]]></category>

		<category><![CDATA[atomic-free]]></category>

		<category><![CDATA[lock-free]]></category>

		<category><![CDATA[obstruction-free]]></category>

		<category><![CDATA[wait-free]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2008/10/09/hello-intel-software-network/</guid>
		<description><![CDATA[Hi, I'm Dmitriy V'jukov, and welcome to my blog.
I'm going to devote this blog to multi-threading, multi-core, synchronization algorithms and all other concerned things. Development of lock-free, wait-free, obstruction-free, atomic-free synchronization algorithms is my hobby. Some of my designs you can see here.
Also, I've developed a tool called Relacy Race Detector, which can be of [...]]]></description>
			<content:encoded><![CDATA[<p>Hi, I'm Dmitriy V'jukov, and welcome to my blog.</p>
<p>I'm going to devote this blog to multi-threading, multi-core, synchronization algorithms and all other concerned things. Development of lock-free, wait-free, obstruction-free, atomic-free synchronization algorithms is my hobby. Some of my designs you can see <a href="http://groups.google.com/group/lock-free" target="_blank">here</a>.</p>
<p>Also, I've developed a tool called <a href="http://groups.google.com/group/relacy" target="_blank">Relacy Race Detector</a>, which can be of help to developers of synchronization algorithms.</p>
<p>Stay tuned!</p>
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		<item>
		<title>Not getting political...</title>
		<link>http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~3/416254857/</link>
		<comments>http://software.intel.com/en-us/blogs/2008/10/09/not-getting-political/#comments</comments>
		<pubDate>Fri, 10 Oct 2008 00:12:29 +0000</pubDate>
		<dc:creator>Amanda Marvel (Intel)</dc:creator>
		
		<category><![CDATA[Academia]]></category>

		<category><![CDATA[energy]]></category>

		<category><![CDATA[Government]]></category>

		<category><![CDATA[Supercomputing]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2008/10/09/not-getting-political/</guid>
		<description><![CDATA[Now, it would probably be in poor taste (and probably violate Intel rules) to use this post as a forum to push my personal political beliefs, so I will clench my teeth and attempt to refrain. It's not new news that the US is in an economic crisis and something needs to be done soon. Very soon. Being [...]]]></description>
			<content:encoded><![CDATA[<p>Now, it would probably be in poor taste (and probably violate Intel rules) to use this post as a forum to push my personal political beliefs, so I will clench my teeth and attempt to refrain. It's not new news that the US is in an economic crisis and something needs to be done soon. Very soon. Being that a lot of my mindshare focuses on small and medium businesses and their health, stealth and wealth, I really do think that they can rally, with the people's and government's support, and be a driving force to pull us out of this economic mess.  One of the top issues facing us today is Energy - our increasing consumption of it and lack of viable/sustainable/wallet-friendly choices. My take on it is that we call upon our top scientists and utilize the unbelievable supercomputing power available at our National Laboratories to generate new techniques, technologies and solutions in conjunction with incentivizing the ideas and genious of many of those in the private sector. Entrepreneurship is a beautiful thing, and there are a lot of brilliant people out there. Given the right government support they can indeed be a driving force and turn new forms of energy in to an economic success.</p>
<p>So how does this relate to Intel?  The answer is: computing power. The energy problems that need to be solved are highly complex, with many variables, and involve math and engineering that are well beyond many people's comprehension. Without solid, speedy, powerful and reliable computing, I doubt we can get good answers quickly enough to pull us out of the hole. So you better believe that we'll continue to do our part by innovating solid and cutting edge technology to feed all you brilliant people out there. Together we can rally, and I thank you in advance for doing your part.</p>
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