I've been monitoring how many developers are watching all of the segments of the video series we've posted on the Take Five site.   It is natural that not everyone will make it to the end, but I'm wondering if there is anything we could do better.

First, I'd like to know if any of these are the causes:
  A) Didn't know series were there
  B) Watched the video from a different page w/out the series navigation
  C) Didn't have time to watch them all
  D) The video, well, just wasn't that interesting
  E) My boss walked by, and I had to quickly switch screens from videos
  F)  Other:  ______________ 

Take a look at two of the series we've posted from the Game Developers Conference:  Optimizing DirectX for Mulicore, or the SkullTrail series with GRIN Software* and UbiSoft*.  Or the very long Confronting ManyCore series.   Once a video is playing in the player at the top of the site, there is a link that says "see Next in series" and/or "see Previous in series" to easily (at least I thought) move from one to the next. 

While you in the player, you can rate the videos, get the embed code and direct links, leave comments, and/or link back to the blogs.

To see more series, they are in "series boxes" on the tabs below the Take Five player.  If you mouse over the numer, you will get a video description. Be sure to click on the blue arrow to see the Virtualization and Community, and coming soon, Open Source tabs. 

I'd love to hear your comments, and answers to the mulitple choice above.  I'm hoping I don't get too many D's.

Happy Friday!

I cannot envision a more exciting time to be working in the technology industry, and especially, at Intel. Tick-tock, multi-core, low power, atom, larrabee, wimax, mids, 45nm are just a few of the potentially game changing strategies and technologies that Intel is driving today. However, none of these breakthroughs will make a big difference in the marketplace unless ISVs can effectively incorporate them into products that deliver real value and excitement to customers. This is the ‘simple’ premise behind ISPP: Make it easy for ISVs to align their products with the Intel roadmap and enjoy increased business success as a result.

In my past life as an engineer, I got a real kick in the pants from creating new SW and hearing feedback from customers about how cool our app was…or sometimes, wasn't! These days my ‘kick’ comes from driving our talented engineering, ISN developer community, and marketing teams to deliver enabling programs that help you and your company to capitalize on Intel's technology leadership. I’m looking forward to sharing my thoughts and ideas about SW enabling in future posts, but am even more eager to hear your feedback about how we can make ISPP work better. Simple enough?

 I am working with some of the brightest folks here at Intel, our subject matter experts and architects, such as Clay Breshears, Michael Wrinn, Bob Chesebrough and Tim Mattson (amongst others).  I will also be working closely with the indomitable Wolfgang Rosenberg, manager of the Intel Academic Community. 

My job is to reach out to educators and researchers around the world, to connect them with Intel experts and to help foster development of a curriculum to educate the next generation of programmers and engineers on the newest compute platforms.

Hopefully, this blog will go a long way to opening up channels of communication 

We have a number of events and initiatives planned for this year. 

We have already started our monthly Academic Community Curriculum Webinar Series.  During these webinars, we discuss the newest curriculum topics.  It is a great way to speak directly with our course architects.  I moderate the series and I very much look forward to speaking with you there soon.

The next in the series is on May 15 on multi-core design patterns.  Please Register below.

 Register or view past event here.

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We are creating quite a few short videos supporting our academic efforts.

 I'm in the process now of filming a series on threading topics with an emphasis on game development and visual computing.  So far only the first title on Optimizing for DirectX is posted, but the rest will be available soon.

Is this type of content useful?  Are there better ways to scale out our knowledge and build conversation?  I'd like to hear that from you.

 I've asked around internally as to how folks like to consume information.  As you might imagine, there were a wide-range of responses.  Tim Mattson just rolled his eyes when I started to talk about videos and webinars.  While he is a great presenter, his own preference is to just download the PowerPoint or code and have done with it.

Others, myself included, prefer a richer content set.  For me, nothing beats the immediacy of a live event.  That is one reason we have our monthly webinars.  I am also quite interested in convening smaller conversations, perhaps using something like Communicator or Live Meeting, to discuss specific topics or curriculum ideas.  Let me know by responding to this blog.

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Finally, I've become very interested in different forms of new media.  I'm often available on Twitter -find me as @psteinb.

I am the owner of the Intel Software Second Life Island. 

IM me on Second Life as Peretz Stine.

Check out our launch video.

Over the last year, we ran an event series on our Second Life island dedicated to engaging engineers and professionals around the world in conversation on this unique environment.  That program, sadly, is ended, but you can still view much of it here:

Are you interested in meeting on Second Life or other virtual worlds?  It can be arranged.

 Well that's enough for now -you have you orders -tell me how best to foster dialogue.  I'll be working as hard as I can, but you are the whole point.  Let's start the conversation.

The Multi-core Training Workshop was held in the National Electrical and Electronic Teaching Base of Wuhan University, China Friday Apr. 11- Thursday Apr. 17, 2008. The workshop was sponsored by Intel and arranged by Wuhan University that brings teachers and scholars together with Intel specialists to make progress in the teaching contents and experience on multi-core related courses. There were approximately 46 attendees from 22 member universities in the China, most of the attendees are titled with associate professor and focus on teaching, and will directly take charge of the curriculum building of Multi-core Related course. All those universities have adopted multi-core content to their syllabus now and will start teaching the multi-core content at Fall 2008. By that time, the undergraduate/graduate students of more than 100 universities in the China will benefit from the Intel Multi-core University Program and, "it is of great meaning to make those future software engineers start understanding the multi-core architecture and multi-threaded programming technologies at university NOW - the multi-core computing era", said by Richard Wang from Intel.

Thanks for the great support from Intel Education Team, Intel SSG, and Intel ISC, it has taken Jolly Wang so much time to prepare for the workshop tomake the event smoothly, Hai Shen and Selwyn You have made some valuable suggestions for the training agenda, Nick Bao, Stanley Wang, Xiaoping Duan and Feilong Huang, have come to the workshop and made wonderful speeches or worked as instructors.

The workshop took 7 days, with 8 class hours per day and 3 hours free lab time per evening, and consists of three panels: the introduction of Intel Multi-core University Program, the multi-core training, and the teaching symposium.

The first panel's presentations focusing on the development of Intel Multi-core University Program in China, Intel Software and Solutions Group (SSG) and, the University Program registration flow were given by Nick Bao and Stanley Wang.

The Training Panel's presentations were delivered by Jianfeng Yang(WHU), Qingsong Shi(ZJU), Xiaoping Duan and Feilong Huang(Intel). Here the Intel standard training module was adopted on this panel and we add some other useful topics such as parallel architecture, MPI. The lab environment was maintained by Yinbo Xie (WHU). The key contents of training panel include:

• Parallel Architecture Parallel Programming Technologies
• Core 2 architecture Threading Concepts
• OpenMP
• Programming with Windows/POSIX threads
• Threaded programming methodology
• Intel Tools
  • Intel Compiler
  • Intel VTune Performance Analyzer
  • Intel MKL
  • Intel Thread Checker
  • Intel Thread Profiler
• Scalability of threaded applications
• MPI
• TBB

At the third panel, we discussed how to integrate multi-core contents to the syllabus, teaching contents and emphasis. Prof Ting Wang of NUDT was invited to give a keynote speech of curriculum building experience of undergraduate course "Compiler Principle", the National Module Curriculum. Presentations by Dr. Qingsong Shi from Zhejiang University and Dr. Jianfeng Yang from Wuhan University delivered the curriculum (Intel-MOE Module Curriculum) building experience to the participations also. And at the symposium, each university and each teacher introduced the curriculum building status of multi-core related course and their research interests. The discussion made the participants understand each other and increased the friendship among faculties.

Curriculum CD and Courseware were donated to the all participating universities, and from the feedback forms, all the attendances were satisfied with the workshop.

A special thank you goes out to all who attended and contributed to a very successful event.

Dave Sekowski: We recently announcement with Sun Microsystems that we have made TBB available on Sun Solaris* using Sun Studio* compilers. What exactly went into the patches we made to TBB?
Chris Huson: One set of changes was the addition of using statements in the test system, to accommodate slight differences in the header files; most of these were incorporated as-is after some discussion. Sun also disabled the "warning is error" switch in the build. We use it to be pedantic about the code, but the Sun compiler found different things to warn about. A change disabling the switch for Sun was put into mainline. The other major change was to add SunOS to the preprocessor statements which were for Linux.

Dave Sekowski: In porting TBB to Sun Solaris with Sun Studio what needed to be changed and why?
Chris Huson: The change needing review on the Sun side was support for the stricter Sun support for standard library functions. Some of these functions are in the global namespace on some platforms, and in the std:: namespace on others (including Sun). Vladimir Polin incorporated Sun's modifications in a way that also supported older platforms, and Sun reviewed and approved those changes.

Dave Sekowski: Can you tell me a little about building it with Sun Studio compilers and working it into our regular build, test and release flow?
Chris Huson: The process was virtually identical to the Linux build, especially after we started using the Sun Studio Express compiler. The system is now being incorporated into our nightly build and test system, with no major problems so far.

Dave Sekowski: Do you have any additional comments on how it went?
Chris Huson: The changes were small, and incorporating them into the current version of TBB was pretty painless.

Dave Sekowski: Finally, what did you think about the collaboration with Sun to make this port happen?
Chris Huson: The Sun developers did a great job in porting TBB to their platform. Because they adhered to the spirit of the design of TBB, incorporating those changes was an easy job.

The interesting feature is how the system is designed to work.  The input spoken word is first translated to text with Automatic Speech Recognition (ASR) software, the text is translated with Spoken Language Translation (SLT) software to the target language, and this text is used to generate spoken output with Text to Speech (TTS) software.  Over the course of the TC-STAR project, translation performance has improved from 40 percent to 60 percent. 

A quad-core processor should be able to handle three applications running in cooperation.  Use of a single processor might even give a performance boost (over three single-core chips) by being able to pipeline results more efficiently.  No details were given in the article on what kind of processors were utilized, but there was mention of using several ASR and SLT systems to improve the translations.  This combination by itself would be a good use of multiple cores.

It will require the cooperation of aliens offering us their SLT and TTS pieces if we're going to be able to build a universal translator based on this technique.  I'm skeptical that dolphins would be able to give us any transcription software.  However, even without opposable thumbs, if we could give them access to water-proof laptops and C++ manuals, who knows what they might come up with.

These are tough problems and I don’t have answers for them yet.  But I have a few ideas and I hope in the next few posts to share them and get community feedback that might inspire some solutions.  So bear with me as I stumble about and maybe we can all learn something.

Anyone who has had much exposure to presentations about Intel TBB has probably heard in one form or another the motto, “process locally, steal globally.”  The Cilk philosophy embodied in the TBB task scheduler is to constrain active threads to their own local region in memory to exploit any memory that may already reside in the caches of the processing element running that thread; meanwhile, idle threads should try to steal work from memory regions as yet untouched by the active thread(s) to avoid interrupting those running threads.

When one of my customers presented an example using a nested pair of parallel_for statements, I realized that all my knowledge on subject of scheduling was theoretical: I hadn’t dug down into the guts of this code.  Now might be the time. 

First, here’s a sketch of the test code.  You’ll note an outer and inner loop with a lock on the outer and some spinning work on the inner.  This is intended to represent the structure of a program operating on a set of objects that block because of some postulated resource contention, and the inner loop represents the work done to compute that shared resource.  You’ll see that the lock is currently commented out.  When running this code on an 8-core machine, it will sometimes lock up.  Some ideas have been bounced around about why, but I’m curious whether I can demonstrate the workings of the problem rather than just speculating about it.  There’s also explicit references to the auto_partitioner, but with the advent of the affinity_partitioner, use of the auto_partitioner has been deprecated.  Still, we’ll start with this one and then see if we can tell the difference when looking under the hood.

So what’s going on here?  As is my wont, I turned to Intel® Thread Profiler for a first look at the processing:

Hrumph!  I can see eight threads cranking at the work, which is good because I’m running on an 8-core processor.  32% of the run time is spent at concurrency level 8.  Most of the time is spent in that serial tail that must represent startup processing, but the whole run is under 0.2 seconds so I suspect that’s a fixed overhead that will be negligible compared to the overall time of real work.  But that’s about all.  Zooming in on the high concurrency zone:

Where the work is done, the test is keeping 8 threads busy 94% of the time. But still there’s no clue about how the task scheduler is dividing the work, though it looks like it gets interesting towards the end of the run. Guess I’ll have to revert to an old standard, inserting print statements to expose what is happening in the code:

Unfortunately, while I can print out the loop bounds that tell me where I am in the nested executions of the array, I can’t print which thread is handling which range.  The TBB task object that might contain that information lies outside the scope of the outer_loop class.  Stuck.

But not for long.  In the evolving library that is Intel Threading Building Blocks, there is a new feature, available in at least the latest open source release (upgraded to Stable as tbb20_20080408oss), called task_scheduler_observer.  I’ve implemented an observer that lets me identify which thread executes which range.  In my next post I will describe it and start exploring the behavior of the scheduler.  Stay tuned!

Given that context, it was startling to hear a panelist at IPDPS (in Miami, a couple of weeks ago) assert that parallel-processing topics have been disappearing from CS curricula in recent years. As anecdotal evidence, he pointed out the topic’s removal in the 2^nd edition of Introduction to Algorithms (the elegant tome otherwise known by its authors’ initials, CLRS).

Could this possibly be true? Before rushing off to blog, I had to check. First, find an old copy of CLRS, oops, CLR in those days. Sure enough, there was a whole chapter called “Algorithms for parallel computers” which had gone missing in the current edition. Hmm, perhaps parallel concepts were infused into the overall approach? After a couple of long evenings getting reacquainted with CLRS, I had to conclude: no, it’s simply disappeared.

But perhaps this example is a weird one-off, a singular anomaly offset by broader trends? After all, schools like UC Berkeley introduce concurrency in the freshman course, and we here at ISC work with many schools on this topic. Further, googling the obvious keywords pops over a million hits, so things would appear to be, reassuringly, busy.

No. The panelist’s observation is accurate. If anything, the situation is worse than described. Here are some unhappy details:

Way back in 1995, IEEE Computer published an article, Parallel Computing in the Undergraduate Curriculum, by profs at Colgate. As stated in the abstract, “The author describes how parallel computing can be integrated into courses throughout the computer science undergraduate curriculum.”

Good stuff. So, what is Colgate doing now, 13 years later? There is one course on the topic, at the advanced level only, and it is NOT required for the CS major.

Still 1995: the First Wellesley Forum on Parallel Computing Curricula. Brown university presents a paper called Integrating Parallelism into the First Theory Course

Good stuff. So, what is Brown doing now, 13 years later? They list a single grad course, offered occasionally -- btw NOT this year.

Forward a couple years, to ITiCSE ’97. George Washington University presents a paper, Concurrent programming CAN be introduced into the lower-level undergraduate curriculum. They even refer back to ACM standardization efforts in this area, from 1991.

Good stuff. So what is GW doing now, 11 years later? At last, something: in one required course, called Software Paradigms, we read among the topics: “concurrent software design paradigms and patterns”. Excellent. I’m going to contact this prof, Michael Feldman, maybe buy him a beer – uh, hold that thought, Feldman is listed as retired…

One more. Forward to the OOPSLA 1998 Educators’ Symposium, where Loyola of Chicago is arguing: “that a computer-science curriculum should introduce the principles of concurrent programming in an integrated, coherent, and application-independent fashion early in the major.”

Good stuff. So, what is Loyola doing now, 10 years later? Sigh. One advanced class, NOT required for the CS major. No evidence of concurrency in other courses.

The pattern is monotonously repetitive. Forward-looking academics looked at the parallel computing challenge a decade ago, announced they would champion a solution, and saw their efforts, for the most part, defeated. What happened??

I’m headed to ITiCSE ’08, in Madrid this summer, to tilt at this windmill myself. Those of us looking to retire the now-obsolete sequential assumptions, baked into 50 years of CS curricula, do enjoy one serious advantage not available to those courageous predecessors: multicore computing platforms are now the norm. Recognizing that reality, let’s make the adjustment time short.